///////////////////////////////
//project: test_fpga_new
//designer: qyw
//decription: pll beh module for testbench
//////////////////////////////////

`timescale 1ns/1ps
module pll(//input
			areset,
			inclk0,
			c0,
			c1,
			c2,
			locked
			);
input		inclk0,			areset;
output		c0,	c1,	c2,   locked;
reg		locked,	clk_1m,	clk_250k,clk_125k;

assign c0 = areset ? 1'b0 : clk_1m;
assign c1 = areset ? 1'b0 : clk_250k;
assign c2 = areset ? 1'b0 : clk_125k;

initial begin
	clk_125k = 1'b0;
	clk_1m = 1'b0;
	clk_250k = 1'b0;
	locked = 1'b0;
	@(posedge areset)
	#3680 locked = 1'b1;
end

always #4000 clk_125k = ~clk_125k;
always #2000 clk_250k = ~clk_250k;
always #500 clk_1m = ~clk_1m;
endmodule
